This invention relates to a semiconductor integrated circuit device and a method of producing the same. More particularly, the present invention relates to integrated circuit devices such as an application specific I.C. (ASIC), a microprocessor, a microcontroller, a digital signal processor, etc., and a method of efficiently producing them.
Systems such as gate arrays, standard cells, cell based ICs, etc., have been widely employed in the past to accomplish a large-scale logic circuit, in particular. A characteristic feature of these integrated circuits is that partial circuits referred to as "cells" are prepared in advance.
The term "cell" means a small scale logic circuit such as NAND, NOR, etc., for which layout of a mask pattern has already been finished. Generally, the positions of input/output terminals and an operation speed are determined besides the mask layout.
When information on this cell is gathered and registered to an auxiliary memory unit of a computer for computer aided design, it is referred to as a "cell library" (or sometimes "macrocell library", "macro library", "device library" and "standard cell library").
If such a cell library for so-called "CAD (Computer Aided Design)" is prepaid in advance, an integrated circuit having an intended logic function can be accomplished by merely disposing the cells on a chip and connecting the terminals of the cells by wirings. Accordingly, the integrated circuit having the intended logic function can be fabricated within a short time because logic design can be carried out without taking a circuit operation on a transistor level and layout into consideration.
A "pass transistor circuit" is another technology associated with the present invention. It is known that when the pass transistor circuits are used, logic such as 2-input AND, OR, exclusive-OR (XOR), etc., can be accomplished in a smaller area and at a higher speed than ordinary CMOS circuits by using the same internal circuit connection and changing the application forms of external 2-input signals and their inverted 2-input signals (that is, two complementary input signals).
A publication, J. H. Pasternak et al IEEE Circuits and Devices, July, 1993, pp. 23-28 and a publication K. Yano et al IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 388-395 (1990) can be cited as the references relating to this pass transistor circuit.
These references describe that in order to constitute 3-input OR, AND, XOR, etc., by using the means of this pass transistor circuit, the internal circuit connection for constituting XOR is different from the internal connection for constituting OR and AND, and that the application form of the 3-input signal for constituting XOR is different from the application form of the 3-input signal for constituting OR and AND.
On the other hand, the article "Speed Performance of Pass Transistor Logic Gate Using CMOS/SIMOX Process" by Y. Kado et al, 1992 The Institute of Electronics Information and Communication Engineers of Japan, Spring Meeting, C-560, pp. 5-181 describes a 2-input NAND/AND gate circuit having improved speed performance wherein an inverter for amplifying an output voltage is connected to a source-drain path of a pass transistor, and when the drain and the gate of one pass transistor are driven by complementary input signals or by the same input signal, speed performance can be improved by setting the drain input signal to a ground level Vss or to a power supply voltage level V.sub.DD.